Host controlled data chip address sequencing for a distributed memory buffer system
US10747442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Feb 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one aspect, the data buffer circuit receives a next to be used store data tag from a Host wherein the store data tag specifies the data buffer location in the data buffer circuit to store data, and in response to receiving store data from the Host, moves the data received at the data buffer circuit into the data buffer pointed to by the previously received store data tag.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.