Vectorization of wide integer data paths into parallel operations with value extraction for maintaining valid guard bands
US10747534B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Feb 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30014
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.