Pooled frontline ECC decoders in memory systems
US10747613B2 · kind B2 · utility
2Cited by
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17Claims
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Key dates
| Filing date | Sep 7, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.