Leveraging chip variability
US10748640B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Apr 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56008
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.