Three-dimensional semiconductor device and method of manufacturing same
US10748815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2019 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Oct 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
The present disclosure relates to three dimensional (3D) transistor structures and methods of forming the same. In an aspect, a method comprises providing a vertical stack of alternating layers of channel material and dummy material, forming a first set of fins on the stack, and forming a second fin above the first set of fins, the second fin extending orthogonal to the first set of fins. Further, the first set of fins is cut into a set of fin portions, using the second fin and a first sidewall spacers as an etch mask, and second sidewall spacers are formed on the second fin. These structures are used to form a 3D structure of channel regions and source/drain regions forming transistor structures. Advantageously, the 3D semiconductor structure is manufactured using a relatively low number of mask layers per transistor which decreases manufacturing costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.