Dynamic biasing to mitigate electrical stress in integrated resistors
US10748818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.