Andrew Strachan
27Patents
5h-index
27Co-inventors
69Inventor score
Filing activity: Mar 30, 1990 → Jun 10, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7180140B1 | PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such device | Electricity | 27 | Expired |
| US8445353B1 | Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device | Electricity | 11 | Active |
| US7067879B1 | Integration of trench power transistors into a 1.5 μm BCD process | Electricity | 7 | Expired |
| US8686502B2 | Schottky diode integrated into LDMOS | Electricity | 5 | Active |
| US5045495A | Forming twin wells in semiconductor devices | Emerging Cross-Sectional Technologies | 5 | Expired |
| US9905428B2 | Split-gate lateral extended drain MOS transistor structure and process | Electricity | 5 | Active |
| US6548839B1 | LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability | Electricity | 5 | Expired |
| US9773777B2 | Low dynamic resistance low capacitance diodes | Electricity | 2 | Active |
| US7510944B1 | Method of forming a MIM capacitor | Electricity | 2 | Active |
| US6798641B1 | Low cost, high density diffusion diode-capacitor | Electricity | 2 | Expired |
| US10431357B2 | Vertically-constructed, temperature-sensing resistors and methods of making the same | Electricity | 1 | Active |
| US8664076B2 | Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density | Electricity | 1 | Active |
| US7071513B1 | Layout optimization of integrated trench VDMOS arrays | Electricity | 1 | Expired |
| US7425741B1 | EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion | Electricity | 1 | Expired |
| US11152505B2 | Drain extended transistor | Electricity | 1 | Active |
| US8541863B2 | Data retention in a single poly EPROM cell | Electricity | 0 | Active |
| US9831135B2 | Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistors | Electricity | 0 | Active |
| US10937574B2 | Vertically-constructed, temperature-sensing resistors and methods of making the same | Electricity | 0 | Active |
| US6646320B1 | Method of forming contact to poly-filled trench isolation region | Electricity | 0 | Expired |
| US10153269B2 | Low dynamic resistance low capacitance diodes | Electricity | 0 | Active |
| US10748818B2 | Dynamic biasing to mitigate electrical stress in integrated resistors | Electricity | 0 | Active |
| US7192853B1 | Method of improving the breakdown voltage of a diffused semiconductor junction | Electricity | 0 | Expired |
| US7560348B2 | Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in | Electricity | 0 | Active |
| US9595480B2 | Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistors | Electricity | 0 | Active |
| US10714594B2 | Transistors with oxide liner in drift region | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.