Integrated circuit for low power SRAM
US10748911B2 · kind B2 · utility
7Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a semiconductor substrate, an active area, a gate electrode, and a butted contact. The active area is oriented in a first direction and has at least one tooth portion extending in a second direction in the semiconductor substrate. The gate electrode overlies the active area and extends in the second direction. The butted contact has a first portion above the gate electrode and a second portion above the active area. A portion of the second portion of the butted contact lands on the tooth portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.