Patent · US Active

Method and apparatus for a phase locked loop circuit

US10749532B1 · kind B1 · utility

2Cited by

4References

20Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Mayank Raj · San Jose, US
Didem Z. Turker Melek · San Jose, US
Parag Upadhyaya · Los Gatos, US
Yohan Frans · Palo Alto, US
Kun-Yung Chang · Los Altos Hills, US

Key dates

Filing date	Mar 4, 2019
Grant date	Aug 18, 2020
Priority date	—
Expiry date	Mar 4, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/22
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO), a first loop circuit, and a second loop circuit. The first loop circuit includes a first loop filter configured to receive a first signal based on a feedback signal from the VCO and provide a first VCO frequency control signal to the VCO. The second loop circuit includes a compensation circuit configured to receive a reference signal and the first signal, and provide a second VCO frequency control signal to the VCO.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.