Memory device and memory system having the same
US10755784B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Mar 15, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device includes: an independent circuit configured to output an independent signal; a memory cell array formed on a top of the independent circuit, the memory cell array including a plurality of memory cells in which data is stored; a revision circuit formed on a top of the memory cell array, the revision circuit storing modified ROM data different from the independent signal, the revision circuit outputting a ROM control signal and the modified ROM data in response to a select signal when an error occurs in the independent signal in a test operation of the independent circuit formed under the memory cell array; and a selection circuit configured to output the independent signal or the modified ROM data in response to the ROM control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.