Method of fabricating semiconductor devices with same conductive type but different threshold voltages
US10755919B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Feb 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing semiconductor devices, including the steps of providing a substrate with a first active region, a second active region and a third active region, forming dummy gates in the first active region, the second active region and the third active region, removing the dummy gates to form trenches in the first active region, the second active region and the third active region, forming a high-k dielectric layer, a first bottom barrier metal layer on the high-k dielectric layer, a second bottom barrier metal layer on the first bottom barrier metal layer, and a first work function metal layer on the second bottom barrier metal layer in the trenches, removing the first work function metal layer from the second active region and the third active region, removing the second bottom barrier metal layer from the third region, and filling up each trench with a low resistance metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.