Warpage control of semiconductor die
US10755995B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 2, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | May 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.