Multi-layer redistribution layer for wafer-level packaging
US10756042B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2016 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Feb 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3841
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Aspects of the embodiments include a semiconductor package that includes a printed circuit board (PCB) and a semiconductor die. The semiconductor die including an interconnect landing pad on an active side of the semiconductor die; a solder material on the interconnect landing pad; a partial redistribution layer on the active side of the semiconductor die; and a protection layer on the partial redistribution layer, the protection layer comprising the solder material. The semiconductor die is electrically connected to the PCB by the solder material on the interconnect landing pad. The partial redistribution layer and the protection layer are separated from the printed circuit board by an air gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.