Device with a high efficiency voltage multiplier
US10756083B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2017 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | May 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/07
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.