Etchant composition, method of manufacturing semiconductor device using the same, and semiconductor device
US10756112B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2020 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Jan 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided herein is a semiconductor device and a method of manufacturing the same. The method includes alternately forming sacrificial layers and interlayer insulating layers on a semiconductor substrate. The method further includes forming a slit to expose the sacrificial layers by etching through the sacrificial layers and the interlayer insulating layers and forming interlayer openings by removing the exposed sacrificial layers. The method also includes depositing a conductive material in the interlayer openings and forming seams in which core patterns are deposited. The method additionally includes oxidizing a portion of the conductive material in the interlayer openings using a wet etching process and forming conductive patterns by removing the oxidized portion of the conductive material from the interlayer openings while leaving the seams intact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.