Patent · US Active

Extended drain MOS with dual well isolation

US10756187B1 · kind B1 · utility

0Cited by
2References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 28, 2019
Grant dateAug 25, 2020
Priority date—
Expiry dateMar 28, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/516
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.