Chin-Yu Tsai
25Patents
10h-index
29Co-inventors
75Inventor score
Filing activity: Nov 20, 1998 → Jul 17, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6137140A | Integrated SCR-LDMOS power device | Electricity | 104 | Expired |
| US6424005B1 | LDMOS power device with oversized dwell | Electricity | 94 | Expired |
| US6512280B2 | Integrated CMOS structure for gate-controlled buried photodiode | Electricity | 72 | Expired |
| US6441431B1 | Lateral double diffused metal oxide semiconductor device | Electricity | 43 | Expired |
| US6548874B1 | Higher voltage transistors for sub micron CMOS processes | Electricity | 43 | Expired |
| US6392263B1 | Integrated structure for reduced leakage and improved fill-factor in CMOS pixel | Electricity | 20 | Expired |
| US6729886B2 | Method of fabricating a drain isolated LDMOS device | Electricity | 18 | Expired |
| US6468849B1 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology | Electricity | 15 | Expired |
| US6753575B2 | Tank-isolated-drain-extended power device | Electricity | 13 | Expired |
| US6680226B2 | Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology | Electricity | 10 | Expired |
| US6413824B1 | METHOD TO PARTIALLY OR COMPLETELY SUPPRESS POCKET IMPLANT IN SELECTIVE CIRCUIT ELEMENTS WITH NO ADDITIONAL MASK IN A CMOS FLOW WHERE SEPARATE MASKING STEPS ARE USED FOR THE DRAIN EXTENSION IMPLANTS FOR THE LOW VOLTAGE AND HIGH VOLTAGE TRANSISTORS | Electricity | 8 | Expired |
| US6274918A | Integrated circuit diode, and method for fabricating same | Electricity | 5 | Expired |
| US6753202B2 | CMOS photodiode having reduced dark current and improved light sensitivity and responsivity | Electricity | 5 | Expired |
| US6784493B2 | Line self protecting multiple output power IC architecture | Electricity | 5 | Expired |
| US6621064B2 | CMOS photodiode having reduced dark current and improved light sensitivity and responsivity | Electricity | 3 | Expired |
| US6770935B2 | Array of transistors with low voltage collector protection | Electricity | 2 | Expired |
| US6709900B2 | Method of fabricating integrated system on a chip protection circuit | Electricity | 2 | Expired |
| US9608109B1 | N-channel demos device | Electricity | 2 | Active |
| US10756187B1 | Extended drain MOS with dual well isolation | Electricity | 0 | Active |
| US6806541B2 | Field effect transistor with improved isolation structures | Electricity | 0 | Expired |
| US11387323B2 | Extended drain MOS with dual well isolation | Electricity | 0 | Active |
| US6730569B2 | Field effect transistor with improved isolation structures | Electricity | 0 | Expired |
| US9947783B2 | P-channel DEMOS device | Electricity | 0 | Active |
| US10505037B2 | P-channel DEMOS device | Electricity | 0 | Active |
| US6710427B2 | Distributed power device with dual function minority carrier reduction | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.