Slave device enhancing data rate of DSI3 bus
US10756925B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Aug 25, 2020 |
| Priority date | — |
| Expiry date | Mar 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed DSI3 slave devices may enhance the data rate of the DSI3 bus using modified nibble encoding, pulse shaping, spectral shaping, and/or message preambles to provide chip time and level tracking. In one embodiment, there is provided a communications method that includes: converting a binary data stream into a ternary unipolar non-return-to-zero level channel signal; and driving the channel signal as an electrical current on a signal conductor. The converting uses an encoder that maps binary nibbles to a set of ternary triplets, each triplet in the set having an average level between 2/3 and 4/3 inclusive, and each triplet including at least one internal transition between levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.