Synchronization of computation engines with non-blocking instructions
US10761822B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Dec 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are systems and methods for generating program code for an integrated circuit, where instructions in the code synchronize computation engines that support non-blocking instructions. In various examples, a computing device can receiving an input data set including operations to be performed by an integrated circuit device and dependencies between the operations. The input data set can include a non-blocking instruction, and an operation that requires that the non-blocking instruction be completed. The computing device can generate instructions for performing the operation including a particular instruction to wait for a value to be set in a register of the integrated circuit device. The computing device can further generate program code including the non-blocking instruction and the instructions for performing the operation, wherein the non-blocking instruction is configured to set the value in the register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.