Drazen Borkovic
41Patents
9h-index
33Co-inventors
75Inventor score
Filing activity: Nov 30, 1999 → Aug 7, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6519753B1 | Programmable device with an embedded portion for receiving a standard circuit design | Electricity | 48 | Expired |
| US7237214B1 | Method and apparatus for circuit partitioning and trace assignment in circuit design | Physics | 25 | Expired |
| US6643829B1 | Reducing clock skew in clock gating circuits | Physics | 19 | Expired |
| US7007254B1 | Method and apparatus for the design and analysis of digital circuits with time division multiplexing | Physics | 17 | Expired |
| US7082582B1 | Reducing clock skew in clock gating circuits | Physics | 9 | Expired |
| US8176452B2 | Method and apparatus for circuit partitioning and trace assignment in circuit design | Physics | 9 | Active |
| US11847507B1 | DMA synchronization using alternating semaphores | Physics | 9 | Active |
| US11561833B1 | Allocation and placement of resources for network computation | Physics | 9 | Active |
| US11003429B1 | Compile-time scheduling | Physics | 9 | Active |
| US7844930B2 | Method and apparatus for circuit partitioning and trace assignment in circuit design | Physics | 8 | Active |
| US8458639B2 | Circuit partitioning and trace assignment in circuit design | Physics | 8 | Active |
| US10846201B1 | Performance debug for networks | Physics | 7 | Active |
| US10761822B1 | Synchronization of computation engines with non-blocking instructions | Physics | 5 | Active |
| US11467946B1 | Breakpoints in neural network accelerator | Physics | 5 | Active |
| US9038013B2 | Circuit partitioning and trace assignment in circuit design | Physics | 4 | Active |
| US11182314B1 | Low latency neural network model loading | Physics | 3 | Active |
| US11610102B1 | Time-based memory allocation for neural network inference | Physics | 3 | Active |
| US11741350B2 | Efficient utilization of processing element array | Physics | 3 | Active |
| US8726219B2 | Analysis of digital circuits with time division multiplexing | Physics | 2 | Active |
| US8479142B2 | Method and apparatus for the design and analysis of digital circuits with time division multiplexing | Physics | 2 | Active |
| US11748622B1 | Saving intermediate outputs of a neural network | Physics | 2 | Active |
| US11221979B1 | Synchronization of DMA transfers for large number of queues | Physics | 2 | Active |
| US10846621B2 | Fast context switching for computational networks | Physics | 2 | Active |
| US11016775B2 | Neural network operation reordering for parallel execution | Physics | 1 | Active |
| US11354130B1 | Efficient race-condition detection | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.