Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit
US10761848B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2020 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Feb 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3838
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for implementing an integrated circuit with core-level predication includes: a plurality of processing cores of an integrated circuit, wherein each of the plurality of cores includes: a predicate stack defined by a plurality of single-bit registers that operate together based on one or more of logical connections and physical connections of the plurality of single-bit registers, wherein: the predicate stack of each of the plurality of processing cores includes a top of stack single-bit register of the plurality of single-bit registers having a bit entry value that controls whether select instructions to the given processing core of the plurality of processing cores is executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.