Securely exposing an accelerator to privileged system components
US10762244B2 · kind B2 · utility
4Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Feb 22, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.