Inventor · Santa Clara, CA, US

Brian S. Morris

42Patents
6h-index
64Co-inventors
72Inventor score

Filing activity: Jan 21, 2005 → Jun 13, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9934143B2 Mapping a physical address differently to different memory devices in a group Physics 73 Active
USD722074S1 Display screen with graphical user interface General 57 Active
USD745880S1 Display screen with graphical user interface General 56 Active
USD722073S1 Display screen with graphical user interface General 52 Active
US9449671B2 Techniques for probabilistic dynamic random access memory row repair Emerging Cross-Sectional Technologies 11 Active
USD524451S1 Railing and sunshade support for a pool General 9 Expired
US10031861B2 Protect non-memory encryption engine (non-mee) metadata in trusted execution environment Physics 6 Active
US9658963B2 Speculative reads in buffered memory Emerging Cross-Sectional Technologies 6 Active
US10163508B2 Supporting multiple memory types in a memory slot Emerging Cross-Sectional Technologies 5 Active
US9269436B2 Techniques for determining victim row addresses in a volatile memory Physics 5 Active
US10762244B2 Securely exposing an accelerator to privileged system components Emerging Cross-Sectional Technologies 4 Active
US10061719B2 Packed write completions Physics 4 Active
US9740646B2 Early identification in transactional buffered memory Physics 4 Active
US9959418B2 Supporting configurable security levels for memory address ranges Physics 3 Active
US7210964B2 Electrical connector backshell assemblies Electricity 3 Expired
US10184882B2 System and method for providing user guidance for electronic device processing Physics 3 Active
US10915468B2 Sharing memory and I/O services between nodes Emerging Cross-Sectional Technologies 3 Active
US10169858B2 System and method for automated cosmetic inspection of electronic devices Physics 3 Active
US10671740B2 Supporting configurable security levels for memory address ranges Physics 3 Active
US9720838B2 Shared buffered memory routing Physics 3 Active
US9824754B2 Techniques for determining victim row addresses in a volatile memory Physics 2 Active
US9910728B2 Method and apparatus for partial cache line sparing Physics 2 Active
US10102886B2 Techniques for probabilistic dynamic random access memory row repair Emerging Cross-Sectional Technologies 2 Active
US9613722B2 Method and apparatus for reverse memory sparing Physics 2 Active
US9201748B2 Virtual device sparing Physics 2 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.