Patent · US Active

Method for forming a multi-level interconnect structure

US10763159B2 · kind B2 · utility

0Cited by

6References

11Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Basoene Briggs · Heverlee, BE
Christopher Wilson · Tervuren, BE
Juergen Boemmels · Heverlee, BE

Key dates

Filing date	Jul 22, 2019
Grant date	Sep 1, 2020
Priority date	—
Expiry date	Jul 22, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/5226
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.