Vertical semiconductor devices and method of manufacturing the same
US10763167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2019 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jan 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical semiconductor device includes a conductive pattern structure in which insulation patterns and conductive patterns alternately and repeatedly stacked on the substrate. The conductive pattern structure includes an edge portion having a stair-stepped shape. Each of the conductive patterns includes a pad region corresponding to an upper surface of a stair in the edge portion. A pad conductive pattern is disposed to contact a portion of an upper surface of the pad region. A mask pattern is disposed on an upper surface of the pad conductive pattern. A contact plug penetrates the mask pattern to contact the pad conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.