Patent · US Active

Memory structure with multi-cell poly pitch

US10763267B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Yew Keong Chong · Austin, US
Sriram Thyagarajan · Austin, US
Munish Kumar · Sindhar, IN

Key dates

Filing date	Jan 9, 2019
Grant date	Sep 1, 2020
Priority date	—
Expiry date	Jan 9, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/412
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.