Yew Keong Chong
93Patents
9h-index
110Co-inventors
81Inventor score
Filing activity: May 6, 1998 → Jul 7, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10083269B2 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Physics | 31 | Active |
| US6894529B1 | Impedance-matched output driver circuits having linear characteristics and enhanced coarse and fine tuning control | Electricity | 23 | Expired |
| US8848412B1 | Ternary content addressable memory | Physics | 17 | Active |
| US8971133B1 | Memory device and method of operation of such a memory device | Physics | 13 | Active |
| US8830783B2 | Improving read stability of a semiconductor memory | Physics | 11 | Active |
| US7262631B2 | Method and apparatus for controlling a voltage level | Electricity | 11 | Expired |
| US9142266B2 | Memory circuitry using write assist voltage boost | Physics | 10 | Active |
| US7123055B1 | Impedance-matched output driver circuits having coarse and fine tuning control | Electricity | 10 | Expired |
| US8045401B2 | Supporting scan functions within memories | Physics | 9 | Active |
| US8134824B2 | Decoupling capacitors | Electricity | 9 | Active |
| US7660186B2 | Memory clock generator having multiple clock modes | Physics | 6 | Active |
| US9147451B2 | Memory device and method of controlling leakage current within such a memory device | Physics | 6 | Active |
| US8947968B2 | Memory having power saving mode | Physics | 5 | Active |
| US11328750B1 | Bitcell architecture with buried ground rail | Electricity | 5 | Active |
| US8988954B2 | Memory device and method of performing a read operation within such a memory device | Physics | 5 | Active |
| US10796053B2 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Physics | 5 | Active |
| US11288432B2 | Computer implemented system and method for generating a layout of a cell defining a circuit component | Physics | 4 | Active |
| US8582340B2 | Word line and power conductor within a metal layer of a memory cell | Electricity | 4 | Active |
| US10978141B1 | Configurable integrated circuits | Physics | 4 | Active |
| US9627022B2 | Double pumped memory techniques | Physics | 3 | Active |
| US11271567B1 | Buried metal technique for critical signal nets | Electricity | 3 | Active |
| US10817420B2 | Apparatus and method to access a memory location | Physics | 3 | Active |
| US10521532B1 | Segmented memory instances | Physics | 3 | Active |
| US8315123B2 | Wordline voltage control within a memory | Physics | 2 | Active |
| US9721624B2 | Memory with multiple write ports | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.