Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods
US10763364B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2020 |
| Grant date | Sep 1, 2020 |
| Priority date | — |
| Expiry date | Jun 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
Abstract
Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.