Protecting a substrate region during fabrication of a FET sensor
US10768138B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N27/4145
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.