Co-optimization of lithographic and etching processes with complementary post exposure bake by laser annealing
US10768532B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Sep 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of co-optimizing lithographic and etching processes for semiconductor fabrication. The method includes determining a first set of locations for a first complementary laser annealing to be performed on. The first complementary laser annealing is performed at the first set of locations on at least a first semiconductor wafer of a plurality of semiconductor wafers. The first complementary laser annealing is performed before or after a first post-exposure baking process for the at least first semiconductor wafer. After an etching process has been performed on at least the first semiconductor wafer, a second set of locations is determined for a second complementary laser annealing to be performed on. The second complementary laser annealing is performed at the second set of locations on at least a second semiconductor wafer of the plurality of semiconductor wafers. The second complementary laser annealing is performed before or after a second post-exposure baking process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.