Automatic moving of probe locations for parasitic extraction
US10769340B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | May 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Probe location candidates for parasitic extraction are identified from geometric elements on a probe layer. The probe layer is a physical layer of a layout design for a circuit design predetermined for placing one or more new probes. The probe location candidates are geometric elements on the probe layer within a boundary of an area having a predetermined size and covering an original probe location or having a distance from the original probe location less than a predetermined value. Moreover, the probe location candidates are conductively connected to the original probe location. One or more new probe locations on the probe location candidates are selected based on predetermined criteria. From the layout design, a parasitic resistance value for parasitic resistance between a geometric element representing a circuit pad or another device pin and the new one or more probe locations is extracted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.