Integrated circuit and fabrication method thereof
US10770345B2 · kind B2 · utility
1Cited by
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20Claims
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Assignee
Inventors
Key dates
| Filing date | Aug 27, 2018 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Aug 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76802
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.