Semi-differential signaling for DSI3 bus enhancement
US10771281B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2019 |
| Grant date | Sep 8, 2020 |
| Priority date | — |
| Expiry date | Nov 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A semi-differential signaling technique as well as bus devices and communication systems that exploit this technique to enhance the performance of the DSI3 bus. In one embodiment, there is provided a DSI3 master device that can be coupled to a DSI3 slave device via a bus having at least a power supply conductor, a power return conductor, and a signal conductor. The master device includes: a power supply node and a power return node that respectively connect to the power supply conductor and the power return conductor to supply power to the slave device; a signal node that connects to the signal conductor; and a driver that drives the signal node relative to a reference voltage midway between voltages of the power supply node and the power return node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.