Flexible hardware engines for handling operating on multidimensional vectors in a video processor
US10776126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Apr 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a scheduler circuit and a processing circuit. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more operators and (ii) schedule the one or more operators in one or more data paths. The processing circuit generally comprises one or more hardware engines configured as the one or more data paths. The one or more hardware engines are generally configured to generate one or more output vectors in response to zero or more input vectors using the operators. At least one of the one or more hardware engines may support input vector dimensions ranging from zero to at least four dimensions. At least one of the one or more hardware engines is implemented solely in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.