Memory-efficient last level cache architecture
US10776270B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Dec 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory-efficient last level cache (LLC) architecture is described. A processor implementing a LLC architecture may include a processor core, a last level cache (LLC) operatively coupled to the processor core, and a cache controller operatively coupled to the LLC. The cache controller is to monitor a bandwidth demand of a channel between the processor core and a dynamic random-access memory (DRAM) device associated with the LLC. The cache controller is further to perform a first defined number of consecutive reads from the DRAM device when the bandwidth demand exceeds a first threshold value and perform a first defined number of consecutive writes of modified lines from the LLC to the DRAM device when the bandwidth demand exceeds the first threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.