Automated region based optimization of chip manufacture
US10776543B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2018 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jun 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technical solutions are described herein for fabrication of a chip with optimized chip design during the logical synthesis phase of the fabrication. An example method includes optimizing, by a physical synthesis system, a chip design for a chip to be fabricated, the optimization performed according to a first performance metric for the entire chip. The method further includes receiving, by the physical synthesis system, a feedback input comprising a region of the chip and a second performance metric associated with the region. The method further includes modifying, by the physical synthesis system, the chip design by optimizing the region of the chip according to the second performance metric. The method further includes sending, by the physical synthesis system, the modified chip design for fabrication of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.