Inventor · Hopewell Junction, NY, US

Alexander J. Suess

38Patents

6h-index

54Co-inventors

72Inventor score

Filing activity: Dec 20, 1999 → Sep 20, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US7117466B2	System and method for correlated process pessimism removal for static timing analysis	Physics	47	Expired
US6615395B1	Method for handling coupling effects in static timing analysis	Physics	40	Expired
US7398491B2	Method for fast incremental calculation of an impact of coupled noise on timing	Physics	10	Active
US7937604B2	Method for generating a skew schedule for a clock distribution network containing gating elements	Physics	8	Active
US9501609B1	Selection of corners and/or margins using statistical static timing analysis of an integrated circuit	Physics	7	Active
US9483604B1	Variable accuracy parameter modeling in statistical timing	Physics	6	Active
US7694254B2	Method, computer program product, and apparatus for static timing with run-time reduction	Physics	5	Active
US9418188B1	Optimizing placement of circuit resources using a globally accessible placement memory	Physics	4	Active
US10558775B2	Memory element graph-based placement in integrated circuit design	Physics	4	Active
US10216875B2	Leverage cycle stealing within optimization flows	Physics	3	Active
US8302049B2	Method for enabling multiple incompatible or costly timing environment for efficient timing closure	Physics	3	Active
US9436791B1	Optimizing placement of circuit resources using a globally accessible placement memory	Physics	3	Active
US10013516B2	Selection of corners and/or margins using statistical static timing analysis of an integrated circuit	Physics	2	Active
US9703914B2	Optimizing placement of circuit resources using a globally accessible placement memory	Physics	1	Active
US9418201B1	Integration of functional analysis and common path pessimism removal in static timing analysis	Physics	1	Active
US9075948B2	Method of improving timing critical cells for physical design in the presence of local placement congestion	Physics	1	Active
US7650246B2	Process and apparatus for estimating circuit delay	Physics	1	Active
US9747400B2	Optimizing placement of circuit resources using a globally accessible placement memory	Physics	1	Active
US9646122B2	Variable accuracy parameter modeling in statistical timing	Physics	1	Active
US10706194B2	Boundary assertion-based power recovery in integrated circuit design	Physics	1	Active
US10902167B1	Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuits	Physics	1	Active
US10540465B2	Leverage cycle stealing within optimization flows	Physics	1	Active
US9785737B2	Parallel multi-threaded common path pessimism removal in multiple paths	Physics	1	Active
US10552562B2	Leverage cycle stealing within optimization flows	Physics	1	Active
US10970447B2	Leverage cycle stealing within optimization flows	Physics	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.