Configuration of a memory device for programming memory cells
US10777277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.