Methods for reducing transfer pattern defects in a semiconductor device
US10777414B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31122
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are methods for reducing transfer pattern defects in a semiconductor device. In some embodiments, a method includes providing a semiconductor device including a plurality of photoresist lines on a stack of layers, wherein the plurality of photoresist lines includes a bridge defect extending between two or more photoresist lines of the plurality of photoresist lines. The method may further include forming a plurality of mask lines by etching a set of trenches in a first layer of the stack of layers, and removing the bridge defect by etching the bridge defect at a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the stack of layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.