Patent · US Active

Using an interconnect bump to traverse through a passivation layer of a semiconductor die

US10777524B2 · kind B2 · utility

0Cited by
11References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 27, 2018
Grant dateSep 15, 2020
Priority date—
Expiry dateAug 27, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/13051
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.