Patent · US Active

Method of simultaneous fabrication of SOI transistors and of transistors on bulk substrate

US10777552B2 · kind B2 · utility

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1References
20Claims
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Assignee

Inventor

Key dates

Filing dateJul 26, 2018
Grant dateSep 15, 2020
Priority date
Expiry dateJul 26, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D87/00

Abstract

The disclosure relates to a method of simultaneous fabrication of an MOS transistor of SOI type, and of first and second transistors on bulk substrate, comprising: a) providing a semiconductor layer on an insulating layer covering a semiconductor substrate; b) forming a mask comprising, above the location of the second transistor, a central opening which is less wide than the second transistor to be formed; c) plumb with the opening, entirely etching the semiconductor layer and insulating layer, hence resulting in remaining portions of the insulating layer at the location of the second transistor; d) growing the semiconductor by epitaxy as far as the upper level of the semiconductor layer; e) forming isolating trenches; and f) forming the gate insulators of the transistors, the gate insulator of the second transistor comprising at least one part of the said remaining portions of the insulating layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.