Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

US10777656B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Tahir Ghani · Portland, US
• Byron Ho · Hillsboro, US
• Curtis W. Ward · Hillsboro, US
• Michael L. Hattendorf · Beaverton, US
• Christopher P. Auth · Portland, US

Key dates

• Filing date: Sep 20, 2019
• Grant date: Sep 15, 2020
• Expiry date: Sep 20, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0149
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.