Reconfigurable data processing pipeline, and method of operating same
US10778228B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 23, 2019 |
| Grant date | Sep 15, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including an FPGA, configurable to process data via a plurality of data processing operations, and an ASIC, electrically coupled to logic circuitry of the FPGA via switch interconnect network thereof. In one embodiment, the ASIC includes a plurality of circuit blocks, each circuit block configurable to process data via a data processing operation, and selection circuitry, coupled to the logic circuitry of the FPGA and the plurality of circuit blocks of the ASIC, configurable to connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a first circuit configuration to perform a first data processing operation, and in situ, connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a second circuit configuration to perform a second data processing operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.