Non-volatile memory apparatus and reading method thereof
US10783032B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2017 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.