Read and logic operation methods for voltage-divider bit-cell memory devices
US10783957B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Mar 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a particular implementation, a method to perform a read operation on a voltage divider bit-cell having first and second transistors and first and second storage elements is disclosed. The method includes: providing a first voltage to a bit-line coupled to the second transistor of the voltage-divider bit-cell; providing a second voltage to a first word-line and providing an electrical grounding to a second word-line; where the first and second word-lines are coupled to the respective first and second resistive memory devices; and determining at least one of first and second data resistances in the respective first and second storage elements based on an output voltage on the bit-line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.