Distributed mode registers in memory devices
US10783968B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jul 23, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.