NAND flash memory with reconfigurable neighbor assisted LLR correction with downsampling and pipelining
US10783972B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2019 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for operating a storage system including memory cells and a memory controller. Each memory cell is an m-bit multi-level cell (MLC), where m is an integer. The method includes performing a soft read operation of a target memory cell and determining a current LLR (log likelihood ratio) value based on result from the soft read operation. The method also includes grouping m-bit cell values of neighboring memory cells and the target memory cell to respective n-bit indices, based on effect of neighboring memory cells on the LLR of the target memory cell, wherein n is an integer and n<m. An LLR compensation value is determined based on the n-bit indices, and a compensated LLR value is determined based on the current LLR value and the LLR compensation value. The method also includes performing soft decoding using the compensated LLR value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.