Method of making a semiconductor component having through-silicon vias
US10784162B2 · kind B2 · utility
1Cited by
54References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Oct 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor component includes etching a substrate to define an opening. The method further includes depositing a first dielectric liner in the opening, wherein the first dielectric liner has a first stress. The method further includes depositing a second dielectric liner over the first dielectric liner, wherein the second dielectric liner has a second stress, and a direction of the first stress is opposite a direction of the second stress. The method further includes depositing a conductive material over the second dielectric liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.