Memory device
US10784217B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2018 |
| Grant date | Sep 22, 2020 |
| Priority date | — |
| Expiry date | Feb 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a circuit having an element on a substrate, an interconnection layer above the circuit and that includes a pad electrode having a region for metal wiring bonding, a plurality of electrode layers between the circuit and the interconnection layer and that are stacked in a first direction from the circuit to the interconnection layer, a semiconductor pillar that extends in the first direction, and a storage film between the electrode layers and the semiconductor pillar. The pad electrode overlaps the circuit element as viewed in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.