Patent · US Active

Integration of a memory transistor into High-k, metal gate CMOS process flow

US10784277B2 · kind B2 · utility

0Cited by
23References
18Claims
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Assignee

Inventor

Key dates

Filing dateJan 4, 2018
Grant dateSep 22, 2020
Priority date—
Expiry dateJan 5, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/021
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET includes a third gate comprising a second type of conductor material, and the first and second conductor materials are different. Other embodiments are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.